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VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Features
* 2.488Gb/s 1:16 Demux with Integrated Clock and Data Recovery * Recovered Clock and Data Available * Monolithic Phase Locked Loop * Digitally Adjustable Serial Data Sampling Point
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
* Differential Low Speed Outputs * Differential/Single-ended Reference Clock * Loss of Lock Detection * Meets SONET OC-48 and SDH STM-16 Jitter Tolerance Requirements
General Description
The VSC8162 combines a clock recovery unit (CRU) with a 1:16 demultiplexer on a single chip to directly generate 16-bit wide data from an incoming 2.488Gb/s NRZ data stream. An on-chip Phase Locked Loop (PLL) generates a 2.488GHz clock which remains phase locked to the incoming data. The incoming data is retimed and demultiplexed to a 16-bit word. A Loss of Lock (LOL) signal indicates gross conditions where incoming data no longer has sufficient transitions to keep the CRU in lock.
VSC8162 Functional Block DIagram
RTDO+ RTDO- DINVERT D0+ D0- DI+ DI- REFCK+ REFCK- Clock Recovery Data Retime Output Register
D15+ D15- PARITY+ PARITY-
5
PADJ[4:0]
Divide by 16
CLK16+ CLK16- CLKO+ CLKO- LOL
NOREF
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
Functional Description
Clock Recovery:
The clock recovery unit (CRU) consists of a phase detector, voltage controlled oscillator (VCO), loop filter and frequency control unit (FCU). The components of the CRU are fully integrated on the VSC8162. A 19.44MHz reference clock (REFCLK) is required for proper operation of the Clock Recovery Unit (CRU). Jitter tolerance of the CRU is well above the SONET and SDH jitter tolerance masks. In addition, the recovered high speed clock is output on the CLKO pins. Incoming data is presented to both the clock recovery circuit and the data retiming circuit. When the CRU is in lock mode, a phase detector circuit is effective. When there is a phase error between the incoming data and the on-chip VCO, the phase detector output raises or lowers the voltage on the loop filter to null the phase difference. The frequency control unit (FCU) monitors the frequency difference between the reference clock, REFCK, and the recovered clock. At the time that the VCO frequency, fVCO, and the 128x REFCK frequency, 128 x fREF, differ by less than 1 MHz, the FCU only passively monitors the frequency difference continuously without sending any corrections to the loop filter. In the event of the loss of an input signal, or if the input is switching randomly, the VCO will drift in one direction. At the time that fVCO and 128 x fREF differ by more than 1 MHz, the FCU will maintain the VCO frequency to be at approximately 1MHz off the frequency of 128 x fREF, and the lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3us and 100us after the interruption of data. When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160us following the restoration of valid data. The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK is more than approximately 25% above or below the expected value.
Retiming:
The retiming decision circuit functions as a D Flip Flop. The recovered clock nominally clocks the decision circuit in the center of the data eye. Internally, the recovered clock is duplicated to create 32 copies, with a phase difference between each of 1/32 of a unit interval. The PADJ[4:0] inputs select which of the 32 phases are to be used to retime the data. Certain lightwave systems employing optical amplifiers suffer from noise in the leading edge of the data eye. Therefore these systems may achieve their lowest Bit Error Rate (BER) by delaying the retiming point until later in the eye. The PADJ inputs can be strapped to generate a fixed delay or the customer can develop a dynamic circuit which can select the optimum retiming point during a training sequence. The retimed high speed data can be monitored using the RTDO pins. Figure 1 and Table 1 indicate how the PADJ pins adjust the sampling point in the data eye. The step size of each unit interval is approximately 12.5ps. The values in Table 1 are not exact and should be used only as an approximation of the expected delay. Due to environmental variations, the actual measured value at any point could vary by as much as +/- 1 step size. It should be noted that PADJ[4:0] = `00000' always corresponds to the sampling center point and that the delay between unit intervals increases monotonically.
Page 2
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
PADJ are ECL compatible inputs (see Table 6). If the pins are left floating, the inputs will default to the logic low state. In order to set to a logic high level, the inputs can be tied directly to VCC without the need for a resistor.
Table 1: Retiming Phase Adjust Settings PADJ4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PADJ3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
PADJ2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
PADJ1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
PADJ0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Degrees From Center
0.00 11.25 22.50 33.75 45.00 56.25 67.50 78.75 90.00 101.25 112.50 123.75 135.00 146.25 157.50 168.75 180.00 -168.75 -157.50 -146.25 -135.00 -123.75 -112.50 -101.25 -90.00 -78.75 -67.50 -56.25 -45.00 -33.75 -22.50 -11.25
PS From Center
0.0 12.6 25.1 37.7 50.2 62.8 75.4 87.9 100.5 113.0 125.6 138.2 150.7 163.3 175.8 188.4 201.0 -188.4 -175.8 -163.3 -150.7 -138.2 -125.6 -113.0 -100.5 -87.9 -75.4 -62.8 -50.2 -37.7 -25.1 -12.6
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
Figure 1: Retiming Offset
DI
Sampling point at the center of the eye PH_ADJ[4:0] = 00000
Sampling point delayed ~50ps from the center of the eye PH_ADJ[4:0] = 00100
1:16 Demultiplexer
The demultiplexer inside of the VSC8162 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock from the high speed clock input. The demultiplexer accepts a serial data stream input (DI+/DI-) at 2.488 Gb/s and deserializes it into 16 parallel differential outputs (D0..D15). The timing parameters of the parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so that CLK16 can be used to clock the destination of D0..D15. The parity output of the demultiplexer is the XOR of all 16 parallel outputs. The DINVERT input is an ECL input (see Table 6) which can be used to invert the sense of the data through the demultiplexer. If DINVERT is left floating, it defaults to the low state, which is the state that corresponds to normal operation (no data inversion).
FILTI, FILTO Pins
The FILTI and FILTO pins are used to provide additional capacitance to the loop filter of the VCO. To optimize the VCO's performance, it is recommended that 0.1F, size 0805 capacitors are connected between the FILTI+ and FILTI- pins, as well as the FILTO+ and FILTO- pins.
Supplies
The VSC8161 is designed to operate with VEE = -5.2V, VTT = -2.0V and VCC = GND (0.0V). However, the part can be operated in an all positive supply environment, or a mixed positive and negative supply environment. To operate in an all positive supply environment, each of the supply voltages must be shifted up by 5.2V such that VEE will now be GND, VTT = +3.2V and VCC = +5.2V. To operate in a mixed positive and negative supply environment, each of the supply voltages must be shifted up by 2.0V such that VTT will now be GND, VEE = -3.2V and VCC = +2.0V. Bear in mind that termination voltages must be adjusted to reflect any shift in supply voltages.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Interface Recommendations
REFCK+, REFCK- Inputs
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC coupled or AC coupled; it can also be driven single-ended or differentially. Figure 2 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary input.
Figure 2: Single-ended AC Coupling for REFCK+, REFCK- Inputs
Chip Boundary
VCC = GND
ZO
CIN
REFCK+ -1.32V -1.32V
RT = ZO R| | = 1k (Approx.) VTT CSE VTT REFCK-
VTT = -2V
CIN TYP = 0.1F CSE TYP = 0.1F for single ended applications. (Capacitor values are selected for REFCLK = 19.44 MHz)
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
High Speed Data Input:
Advance Product Information
VSC8162
The data input receiver is internally terminated with a 100 ohm resistor between the true and complement inputs. The inputs are internally biased to allow AC coupling. These inputs are recommended to be AC coupled to permit use with a variety of limiting amplifiers. See Figure 3.
Figure 3: High-Speed Data Input Termination
Limiting Amp
8162
Zo = 50
0.1 F
DI
100
Zo = 50
0.1 F
DIN
High Speed Data Output:
A high speed data output termination scheme is shown in Figure 4. In order to disable the high speed data switching, the 422 pulldown resistors can be removed.
Figure 4: High-Speed Data Output Termination
8162
VEE 422 0.1 F
Laser Driver
VTERM 50
DO DON
0.1 F
Zo = 50
422 VEE
50
VTERM
Page 6
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
High Speed Clock Output
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
The high speed clock output is provided for test and measurement purposes. A termination method for the high speed clock output is shown in Figure 5. In addition to the AC coupling method shown, the device may also be DC coupled with a 50 resistor connected to VCC. By using these termination methods, a nominal voltage swing of 200mV - 300mV, single-ended peak-to-peak, can be expected. In order to reduce noise on the board, the clock output can be disabled by using the CKOE pin. CKOE is a normal ECL input, which, when left floating, will default to a low level (output disabled). In order to set the CKOE pin to a logic high, it can be tied directly to VCC without the need for a resistor.
Figure 5: High-Speed Clock Output Termination
8162
VCC VTERM
Zo = 50 0.1 uF 50
CLK CLKN
270
270
Zo = 50
0.1 uF
50
VCC
VTERM
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
D[0-15]+/-, PARITY+/-, CLK16+/- Outputs:
Advance Product Information
VSC8162
The D[0:15]+/-, PARITY+/-, and CLK16+/- output drivers are special-purpose output drivers designed for low power dissipation. Four possible termination schemes are shown in Figures 6, 7, 8, and 9. Figures 6 and 7 are the preferred termination methods. Figure 6 indicates a DC-differential termination method, and Figure 7 is true differential termination. For interfacing the VSC8162 device directly to a VSC8161, Figure 6 is preferred since the DC differential method does not force a DC common mode level at the receiver. The VSC8161 input receivers have internal DC bias resistor that allow them to set their own DC bias level.
Figure 6: Low-Speed Output Termination #1
8162
Receiving Device
Zo = 50
0.1 F
50 50 0.1 F
Zo = 50
0.1 F
Figure 7: Low-Speed Output Termination #2
8162
Receiving Device
Zo = 50
0.1 F 100
Zo = 50
0.1 F
Page 8
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Figure 8 is a DC coupled termination method and provides the best low frequency response. For applications with low data transition density, a DC coupling termination such as that shown in Figure 6 may be required.
Figure 8: Low-Speed Output Termination #3
8162
-1.1V Zo = 50 50
Receiving Device
Zo = 50
50 -1.1V
Figure 9 is provided to show that after the AC coupling capacitors, the 50 termination resistors can be terminated to any DC voltage, shown in Figure 9 by the ground symbol. Please note that Figure 9 will not work when interfacing the VSC8162 directly to the VSC8161.
Figure 9: Low-Speed Output Termination #4
8162
Receiving Device
Zo = 50
0.1 F
50
Zo = 50
0.1 F
50
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
AC Characteristics (Over recommended operating conditions)
Table 2: High Speed Clock and Data Outputs Timing Characteristics Parameters
tpd tDH tr,tf tr,tf
Description
Center of output data eye from falling edge of CLKO+ CLKO period RTDO rise and fall times CLKO rise and fall times
Min
-75 -- -- --
Typ
-- 401.9 -- --
Max
+75 -- 150 135
Units
ps ps ps. ps -- --
Conditions
20% to 80% into 50 load. 20% to 80% into 50 load.
Figure 10: VSC8162 High Speed Output Interface
tDH
CLKO+
High Speed Clock Output tpd
RTDO+/-
Retimed Data Output
tDH
Table 3:
D[0-15]+/-, PARITY+/-, CLK16+/- Output Specifications Description
Output level Output Rise/Fall Times Clock-to-Data CLK16 duty cycle CLK16 period
Parameters
VDIFF tr,tf tCQ tDC tD
MIN
600 -- -0.2 45 --
Typ
-- -- -- -- 6.4
MAX
1100 1200 1.8 55 --
Unit
mV ps ns % ns --
Conditions
20% to 80% into 50 load -- -- --
Figure 11: VSC8162 Parallel Interface
tD
DI+/High speed differential serial data input
D0
D1 D2
D3 D4
D5 D6 D7 D8
D9 D10 D11 D12 D13 D14 D15
Serialized Data tD
CLK16+
Parallel data clock output tCQ
D(0...15),PARITY
Parallel data outputs
VALID DATA (1)
VALID DATA (2)
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G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Table 4: PLL Parameters Parameters
RCd RCf fRC tACQ tset tclr tdensity tjitter ttolerance
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Description
REFCK Duty Cycle REFCK Frequency REFCK Frequency Tolerance Acquisition time Loss of Lock set time Loss of Lock clear time Maximum zero-timing-content period Jitter generationa Jitter toleranceb
Min
45 -- -100 -- 2.3 125 -- --
Typ
-- 19.44 -- -- -- -- 1200 3.6
Max
55 -- +100 20 100 250 -- 4.0
Units
% MHz ppm s s s UI ps rms -- -- --
Conditions
With valid reference clock From data interruption From data restoration For 0 BER -- --
Exceeds mask in Figure 9
a. Measured at the HS clock output for jitter in the 12 kHz to 20 MHz band. Assume 1.2 ps rms input data jitter b. Error-free operation guaranteed when electrical input signal is subject to jitter specified by mask in Figure 9.
Figure 12:
VSC8162 Jitter Mask Specification
slope = -20 dB/decade sinusoidal input jitter amplitude (UI p-p)
30 15
3.0 1.5
VSC8162 Mask SONET/SDH Mask
0.30 0.15
10
600
6k
100k
1000k
frequency (Hz)
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
DC Characteristics (Over Recommended Operating Conditions)
Table 5: High Speed Data and Clock Inputs and Outputs Parameters VDIFF VCM RIN
VOD
Description Serial input absolute voltage differential peak-to-peak swing (DI) Input common mode range Input Resistance between DI+ and DIData Output voltage swing Data Output common mode Clock Output voltage swing Clock Output common mode
Min
200 -1.6 80 600 -1.6 100 -0.2
Typ
-- -- 100 -- -- -- --
Max
1200 -1 120 1200 -1 300 0
Units
mV V Ohm mV V mV V -- -- -- -- -- -- --
Conditions
VODCM
VOC
VOCCM
Table 6: Low Speed ECL Inputs and Outputs Parameters VOH VOL VIH VIL IIH IIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Min
-1100 VTT -1040 VTT -- -50
Typ
-- -- -- -- -- --
Max
-700 -1620 -600 -1600 200 --
Units
mV mV mV mV A A
Conditions 50 ohms to VTT 50 ohms to VTT
-- -- -- --
Table 7: Power Supply Parameters Description Supply voltage Supply voltage Power dissipation Supply Current Supply Current Min
-5.46 -2.1 -- -- --
Typ
-- -- -- -- --
Max
-4.94 -1.9 4.2 620 380
Units
V V W mA mA -- --
Conditions
VEE VTT PD IEE ITT
Outputs open Outputs open Outputs open
Page 12
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Absolute Maximum Ratings1
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Power Supply Voltage, (VEE) .................................................................................................. -7V to VCC+0.5V Power Supply Voltage, (VTT) ............................................................................................................ -3V to 0.5V DC Input Voltage (Differential inputs) .........................................................................................-2.5V to +0.5V Output Current (Differential Outputs)....................................................................................................+/-50mA Case Temperature Under Bias ......................................................................................................-55o to +125oC Storage Temperature.................................................................................................................. -65oC to +150oC
Recommended Operating Conditions
Power Supply Voltage, (VEE) ...............................................................................................................-5.2V+5% Power Supply Voltage, (VTT) ...............................................................................................................-2.0V+5% Operating Temperature Range ...........................................................0oC Ambient to +85oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 13
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
Package Pin Descriptions
Figure 13: Package Pin Diagram
128 127
126
125 124
123 122
121
120 119
118
117 116
115
114 113 112 111
110
109 108 107
106
105
104
VCC VCC NC VCC VEE VCC VCC VEE VCC VEE VCC RTDORTDO+ VCC VEE VCC VEE VCC DIDI+ VCC NC VEE VEEANA VCCANA PADJ4 PADJ3 PADJ2 PADJ1 PADJ0 VTT NC NC NC NC NC VCC VCC
103
VEE VCC CLKOCLKO+ VCC VEE VTT CKOE DINVERT NC REFCK+ REFCKVTT VCC VTT CLK16CLK16+ VTT D0D0+ VTT VCC D1D1+ D2D2+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VCC VTT VTT D3D3+ D4D4+ VCC VTT D5D5+ D6D6+ VCC VTT VTT D7D7+ D8D8+ VTT VCC D9D9+ D10D10+ VTT VCC D11D11+ D12D12+ VTT VTT VCC VCC NC VSUB
39 40
41
42 43
44 45
46
47 48
49
50 51
52
53 54 55 56
57
58 59 60
61
62
63
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FILTO+ FILTI+ FILTIFILTOVEEANA VCCANA VCC NC NC NC NC LOL NOREF VTT VTT VCC PARITY+ PARITYD15+ D15VCC VTT D14+ D14D13+ D13-
64
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Table 8: Package Pin Identification
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Signal Name
VCC VCC NC VCC VEE VCC VCC VEE VCC VEE VCC RTDORTDO+ VCC VEE VCC VEE VCC DIDI+ VCC NC VEE VEEANA VCCANA PADJ4 PADJ3 PADJ2 PADJ1 PADJ0 VTT NC NC NC NC NC
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
I/O
O O I I I I I I I Power supply (GND typ.) Power supply (GND typ.). Do not connect, leave open Power supply (GND typ.) Power supply (-5.2V typ.) Power supply (GND typ.) Power supply (GND typ.) Power supply (-5.2V typ.) Power supply (GND typ.) Power supply (-5.2V typ.) Power supply (GND typ.)
Description
High speed data output (complement) High speed data output (true) Power supply (GND typ.) Power supply (-5.2V typ.) Power supply (GND typ.) Power supply (-5.2V typ.) Power supply (GND typ.) High speed data input (complement) High speed data input (true) Power supply (GND typ.) Do not connect, leave open Power supply (-5.2V typ.) Power supply for analog circuits (-5.2V typ.) Power supply for analog circuits (GND typ.) Decision circuit phase adjust Decision circuit phase adjust Decision circuit phase adjust Decision circuit phase adjust Decision circuit phase adjust Power supply (-2.0V typ.) Do not connect, leave open Do not connect, leave open Do not connect, leave open Do not connect, leave open Do not connect, leave open
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Signal Name
VCC VCC FILTO+ FILTI+ FILTIFILTOVEEANA VCCANA VCC NC NC NC NC LOL NOREF VTT VTT VCC PARITY+ PARITYD15+ D15VCC VTT D14+ D14D13+ D13VSUB NC VCC VCC VTT VTT D12+ D12D11+ D11VCC
Advance Product Information
VSC8162
Description
Power supply (GND typ.) Power supply (GND typ.) Connect to FILTI+ with 0.1 F, 0805 capacitor Connect to FILTO+ with 0.1 F, 0805 capacitor Connect to FILTO- with 0.1 F, 0805 capacitor Connect to FILTI- with 0.1 F, 0805 capacitor Power supply for analog circuits (-5.2V typ.) Power supply for analog circuits (GND typ.) Power supply (GND typ.) Do not connect, leave open Do not connect, leave open Do not connect, leave open Do not connect, leave open Loss of lock Loss of reference Power supply (-2.0V typ.) Power supply (-2.0V typ.) Power supply (GND typ.) Parity bit (true) Parity bit (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (GND typ.) Power supply (-2.0V typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Substrate Voltage (connect to lowest supply voltage, i.e., VEE) Do not connect, leave open Power supply (GND typ.) Power supply (GND typ.) Power supply (-2.0V typ.) Power supply (-2.0V typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (GND typ.)
Pin #
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
I/O
I/O I/O I/O I/O O O O O O O O O O O O O O O -
Page 16
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Signal Name
VTT D10+ D10D9+ D9VCC VTT D8+ D8D7+ D7VTT VTT VCC D6+ D6D5+ D5VTT VCC D4+ D4D3+ D3VTT VTT VCC D2+ D2D1+ D1VCC VTT D0+ D0VTT CLK16+ CLK16VTT
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Description
Pin #
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114
I/O
O O O O O O O O O O O O O O O O O O O O O O O O Power supply (-2.0V typ.)
Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (GND typ.) Power supply (-2.0V typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (-2.0V typ.) Power supply (-2.0V typ.) Power supply (GND typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (-2.0V typ.) Power supply (GND typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (-2.0V typ.) Power supply (-2.0V typ.) Power supply (GND typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (GND typ.) Power supply (-2.0V typ.) Low-speed Differential Parallel Data (true) Low-speed Differential Parallel Data (complement) Power supply (-2.0V typ.) Low-speed clock f = 155.52 MHz (true) Low-speed clock f = 155.52 MHz (complement) Power supply (-2.0V typ.)
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Signal Name
VCC VTT REFCKREFCK+ NC DINVERT CKOE VTT VEE VCC CLKO+ CLKOVCC VEE
Advance Product Information
VSC8162
Description
Power supply (GND typ.) Power supply (-2.0V typ.) 19.44 MHz Reference Clock (complement) 19.44 MHz Reference Clock (true) Do not connect, leave open Invert Parallel Data Outputs (Logic High = Invert) Test input (logic high enables 2.488 GHz clock output) Power supply (-2.0V typ.) Power supply (-5.2V typ.) Power supply (GND typ.) Test signal - low-swing high speed clock output (true) Test signal - low-swing high speed clock output (complement) Power supply (GND typ.) Power supply (-5.2V typ.)
Pin #
115 116 117 118 119 120 121 122 123 124 125 126 127 128
I/O
I I I I O O -
Table 9: Power Supply Summary Signal Name
VEE VEEANA VTT
Pin #
5,8,10,15,17,23,123,128 24,43 31,52,53,60,69,70,76, 82,87,88,94,100,101, 108,111,114,116,122 1,2,4,6,7,9,11,14,16,18, 21,37,38,45,54,59,67, 68,75,81,89,95,102,107, 115,124,127 25,44 65 Power supply (-5.2V typ.)
Description
Power supply for analog circuits (-5.2 typ.) Power supply (-2.0V typ.)
VCC VCCANA VSUB
Power supply (GND typ.) Power supply for analog circuits (GND typ.) Substrate Voltage (connect to lowest supply voltage, i.e., VEE)
All supplies which reference the same voltage may be connected to the same power supply plane. The VCCANA, and VEEANA are noise sensitive supplies. Appropriate power supply noise suppression should be applied to optimize the performance of the device.
Page 18
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC8162
Package Information
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
128 PQFP Package Drawings
PIN 128 PIN 1 PIN 102
Key
RAD. 2.92 .50 (2)
mm
2.35 0.25 2.00 17.20 14.00 23.20 20.00 .88 .50 .22 0-7 .30 .20
Tolerance
MAX MAX +.10 .20 .10 .20 .10 +.15/-.10 BASIC .05 TYP TYP
A A1 A2
E1 E
D D1 E
EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK
2.54 .50
E1 L e b
PIN 64
PIN 38 D1 D TOP VIEW 10 TYP.
R R1
A2
A
A1 10 TYP.
e
R
R1
1
STANDOFF
A
Notes: 1) 2) 3) Drawing is not to scale All dimensions in mm Package represented is also used for the 64, 80, & 100 PQFP packages. Pin count drawn does not reflect the 128 Package.
.25
A1
0.17
MAX.
b
LEAD COPLANARITY
L
NOTES: Package #: 101-322-5 Issue #: 2
G52209-0, Rev. 2.0
9/14/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 19
VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery
Advance Product Information
VSC8162
Notice
This document contains information about a product during its fabrication or early sampling phase of development. The information contained in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
Page 20
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52209-0, Rev. 2.0
9/14/98

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